This invention relates to sigma delta modulators, and more particularly to high speed, low power sigma delta modulators.
As is known in the art, sigma delta modulators have a wide variety of applications, such as in analog to digital converters (ADCs). The modulator operates at a relatively high rate compared to the Nyquist rate in converting an analog input signal into a stream of typically one bit digital signals. In the ADC application, the stream of bits is fed to a decimation filter to produce a series of multi-bit digital words at the converters sampling rate, fs. More particularly, ADC includes a modulator and a decimator. The modulator converts an input voltage into a one-bit data stream at a rate determined by the sampling frequency KfS. The modulator performs oversampling and noise shaping on the input voltage. The one-bit data stream is provided to decimator which low-pass filters the data stream to reduce the quantization noise component thereof, and provides filtered N-bit output samples at a rate fS. In short, the decimator decimates, by a factor K, the one-bit data stream.
In many applications there is a requirement for very low power, (i.e., less than 5 milli-watts as may be provided by batteries), high resolution (i.e., 16 bit digital words) ADCs.
A sigma delta modulator is provided having an integrator with a first input for coupling to an analog signal and a second input for coupling to a reference voltage. A comparator is provided having a first input coupled to an output of the integrator and a second input for coupling to the reference voltage. The comparator produces signal having a logic state in accordance with the relative magnitude of signals at the first and second inputs thereof. The logic state is latched at the output of such comparator during latching transitions in a series of latching pulses fed to the comparator. A one-bit quantizer is provided for storing the logic state of the output of the comparator at sampling transitions of a series of clock pulses fed to the one-bit quantizer. The series of clock pulses and the series of latching pulses are synchronized one with the other. Each one of the latching transitions occurs prior to a corresponding one of the sampling transitions.
In one embodiment, a buffer is coupled between an output of the quantizer and the first input of the integrator.
In one embodiment, the modulator includes a voltage regulator. The regulator produces a voltage to power the buffer. The reference voltage is the voltage produced by the regulator for the buffer.
In one embodiment, the modulator including a second integrator having a first input coupled to the output of the first integrator, a second input for coupling to the reference voltage, and an output coupled to the first input of the comparator. A second buffer is included coupled between an output of the quantizer and the first input of the second integrator.
In one embodiment, the first and second buffers are CMOS inverters used to charge the first and second integrators, respectively.